`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/12/06 19:14:13
// Design Name: 
// Module Name: blinker_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module blinker_sim();
    reg clk_i = 'b0;
    reg [2:0] blink_ctrl = 'b000;
    wire blink_pulse;
    
    blinker UUT(
        clk_i,
        blink_ctrl,
        blink_pulse
    );
    
    always #1 begin clk_i = ~clk_i; end
        
    initial begin
        #10 blink_ctrl <= 'b100;
    end
endmodule
